CMOS integrated circuit chips including a plurality of multiple-element electrical paths, to each of which the same signal is applied, are well known in the art. A typical example comprises two paths intended for producing a pair of clock signals, one of the clock signals being the complement of the other. Each path includes a separate plurality of inverters connected electrically in a cascaded arrangement--one path typically including an odd number of cascaded inverters, the other path typically containing an even number--to produce clock signals that are complementary. A single clock signal is applied simultaneously as input to each of such paths for later recombination at either a clocked gate or a clocked storage device--i.e., a logic gate or a storage device (e.g., a D-type latch) whose timing is controlled by the pair of clock signals.
Multipaths of this type are characterized by signal propagation delays that suffer from uncontrolled variations. Especially serious are the variations in the delays that are caused by uncontrolled variations in certain semiconductor processing parameters. These variations in propagation delays cause skew, thus undesirably reducing the maximum clock rate at which such circuits are capable of operating. In this connection, the term "skew" refers either to the discrepancy between the actual time of arrival of a signal pulse edge and the expected time of its arrival or the discrepancy between the actual times of arrival of two signals which are supposed to arrive simultaneously.
For example, in the case of CMOS circuits containing PFETs and NFETs, as a result of certain kinds of variations in certain ones of the processing parameters, the delays in PFETs and NFETs are affected in the same way, so that little if any discrepancy occurs in the signal propagation delays as between two given paths; whereas as a result of other variations in processing parameters ("worst-case variations") the delays in PFETs and NFETs are affected in opposite ways, so that a relatively large discrepancy occurs in such delays as between the two paths. In present-day art, to obtain a minimum skew circuit design the sum of the delays of one path are set to equal the sum of the delays in the other under only a given set of processing conditions. But this setting of the total delays of one path equal to the total in the other, does not correct for process-induced variations in delays caused by variations in processing parameters that are more likely to be encountered in practice, and certainly does not correct for "worst-case" processing variations.